The present invention relates generally to increasing the resolution of a digital-to-analog converter (DAC) having a predetermined number of bits, and more particularly, to signal level shift shifting circuitry and corresponding methodology in a dual resistor ladder DAC.
Important considerations in designing a DAC usually include determining and obtaining both a required amount of resolution, which relates to differential nonlinearity (DNL), and required amount of accuracy, which relates to integral nonlinearity (INL). Other important considerations include the required operating speed, component count, integrated circuit chip area, current consumption, and power dissipation of the DAC. An appropriate DAC architecture may be chosen from various options depending on application requirements and specifications. A dual resistor ladder architecture is usually chosen for some applications, for example in a voice coil motor position control loop of a hard disk drive servo integrated circuit. Monotonicity is a basic requirement for the DAC of a control loop, and is inherently provided by a dual resistor ladder DAC (because the resistors used in the resistor ladders never have negative resistance).
In a dual resistor ladder DAC, the known technique of increasing DAC resolution by 1 bit usually requires doubling the number of resistors in either a coarse ladder or a fine ladder of the dual resistor ladder DAC. Doubling the number of resistors doubles the impedance and also the parasitic capacitance of the ladders in the DAC, and consequently degrades its operating speed and increases its silicon area cost. See U.S. Pat. No. 5,808,576 entitled “Resistor String Digital-to-Analog Converter”, issued Sep. 15, 1998 to James Chloupek, Henry Tin-Hang Yung and Steven Wiyi Yang. This reference discloses a basic bit-shifting technique to increase resolution in a resistor string DAC having a fixed number of string resistors.
Also see commonly assigned U.S. Pat. No. 7,372,387 entitled “Digital-to-Analog Converter with Triode Region Transistors in Resistor/Switch Network”, issued May 13, 2008 to Qunying Li and Juergen Luebbe, and entirely incorporated herein by reference. This reference discloses use of series-connected MOSFETs operating in their deep triode regions as resistive elements in the fine ladder section of a dual resistor ladder.
FIG. 1 illustrates the architecture of a dual resistor ladder DAC 10-1 including a 6 bit coarse ladder 4 and an 8 bit fine ladder 5. Coarse ladder 4 includes 64 poly (polycrystalline silicon) resistors of resistance R1 connected in series between Vref+ on conductor 2-64 and Vref-on conductor 2-0. The various nodes between the 64 resistors R1 are connected to conductors 2-1, 2-2, . . . , 2-N, . . . , 2-63, respectively, wherein the node number N may be any integer between 0 and 63. The left terminal of each of switches SW(0), SW(1), . . . , SW(N), . . . , SW (63), and SW(64) is connected to a corresponding conductor 2-0, 2-1, 2-2, . . . , 2-N, . . . , 2-63, and 2-64, respectively, where N may be any integer between 0 and 64. The right terminal of each of switches SW(0), SW(1), . . . , SW(N−1), SW(N), SW(N+1), . . . , SW (63), and SW(64) is connected to a corresponding conductor 3-0, 3-1, . . . , 3-(N−1), 3-N, 3-(N+1), 3-63, and 3-64, respectively.
Fine ladder 5 includes 255 poly resistors of resistance R2 connected in series between the right terminal of one of switches SW(0), SW(1), . . . , SW(64) having its left terminal connected to the upper node of a selected resistor 14 of the 64 resistors R1 in coarse ladder 4 and the right terminal of another of switches SW(0), SW(1), . . . , SW(64) having its left terminal connected to the lower node of selected resistor 14 in coarse ladder 4. (Of course, selected resistor 14 may be any of the 64 resistors R1.) In the example shown in FIG. 1, fine ladder 5 is illustrated as being connected between conductors 3-N and 3-(N+1), where N may be any integer between 0 and 63. The various nodes between the 255 resistors R2 are connected to conductors 7-1, 7-2, . . . , 07-253, and 7-254, respectively. The left terminal of each of switches S(0), S(1), . . . , S(254), and S(255) is connected to a corresponding conductor 3-N, 7-1, 7-2, 7-254, and 3-(N+1), respectively, where N may be any integer between 0 and 255. The right terminal of each of switches S(0), S(1), . . . , S(254), and S(255) is connected to DAC output conductor 3.
The switches connected to coarse ladder 4 are actuated by corresponding output conductors 17 of a 6 bit MSB digital decoder 6, and the switches S(0), S(1), . . . , S(254), and S(255) connected to of fine ladder 5 are actuated by corresponding output conductors 18 of an 8 bit LSB digital decoder 8. A 14 bit digital bus 12 supplies the 6 MSBs DIN<13:8> of a digital input code DIN<13:0> to MSB decoder 6, and also supplies the 8 LSBs DIN<7:0> of a digital input code DIN<13:0> to LSB decoder 6.
When fine ladder 5 is shunted between nodes N and N+1 with a selected R1 resistor 14, and the various switches are implemented by means of MOS transistors, the “ON” channel resistance RDS(ON) of each of switches SW(N) and SW(N+1) is considered as half of one “minimum step unit resistance” in fine ladder 5. The ON channel resistance RDS(ON) of each of switches SW(N) and SW(N+1) is equal to (½)*R2.
Thus, switches SW(0), SW(1) . . . SW(64) (which usually are MOS transistor switches) are used to selectively connect any 2 adjacent nodes of the group 2-0, 2-1 . . . 2-64 in coarse ladder 4 with the upper and lower end terminals, respectively, of fine ladder 5. During circuit operation, fine ladder 5 is switched so as to be shunted with the one of the “R1” resistors of coarse ladder 4 that is presently selected by MSB decoder 6. In the present example, R1 resistor 14 between node N and node (N+1) is selected, i.e., connected in parallel with fine ladder 5, by closing the two switches SW(N) and SW(N+1) associated with R1 resistor 14 while opening all of the other switches connected to coarse ladder 4. Therefore, the voltage drop across the chosen coarse ladder resistor 14 is applied across the series connection of the “R2” resistors of fine ladder 5.
One of the many node signal levels within fine ladder 5 is selected in response to 8 bit LSB decoder 8 and passed to DAC output conductor 3 by closing the one of switches S(0), S(1), . . . , and S(255) associated with the selected node while opening all of the others.
Prior Art FIG. 2A indicates a way to improve or optimize the trade-off between resolution and speed performance of DAC 10-1 of Prior Art FIG. 1 without having to resort to the previously mentioned doubling or quadrupling, etc., of the number of poly resistors and without the associated doubling or quadrupling, etc., of the impedance and capacitance of DAC 10-1. Dual resistor ladder DAC 10-2 of Prior Art FIG. 2A includes all of the circuitry of DAC 10-1 of Prior Art FIG. 1, and fine ladder 5 further includes one additional poly “R2 resistor” 21 of resistance R2 connected between conductor 3-(N+1) and one terminal of a switch 25 which has its other terminal connected to conductor 7-254. Another additional poly R2 resistor 22 of resistance R2 is connected between conductor 7-1 and one terminal of a switch 24 which has its other terminal connected to conductor 3-N. DAC 10-2 of FIG. 2A also includes an additional 1-bit “shift bit” decoder 15 which has 2 output conductors 19. One of the 2 conductors 19 is connected so as to control switch 25 and the other conductor 19 is connected so as to control switch 24.
Digital bus 12-1 is a 15-bit bus which supplies the 6 MSBs DIN<14:9> of a 15 bit digital input code DIN<14:0> to MSB decoder 6, supplies the 6 LSBs DIN<8:1> of digital input code DIN<14:0> to LSB decoder 8, and supplies a single shift bit b<0> to shift bit decoder 15.
The basic technique used in DAC 10-2 of FIG. 2A is to shunt or couple an equal R2 resistance 21 in parallel with the top R2 resistor 20 and another R2 resistance 22 in parallel with the bottom R2 resistor 23 of fine ladder 5 in a “complementary manner” such that a 0.5 LSB step of the original 14 bit DAC is created. The 14 bit DAC 10-2 in FIG. 2A provides “0.5 bit level shifting” which in effect extends the 14 bit DAC of FIG. 1 to a 15 bit DAC without doubling the number of resistors in either coarse ladder 4 or fine ladder 5 and without doubling the output impedance and output capacitance of DAC 10-2.
Note that dual resistor ladder DAC 10-2 is a resistive circuit, and if its resolution is to be extended by 1 bit by doubling the number of its fine ladder resistors, the DAC output impedance is nearly doubled, and similarly for the DC parasitic output capacitance. That causes the RC time constant at the DAC output 3 to be much longer, resulting in slower DAC operation. In contrast, if the foregoing level shift method is used and the DAC resolution is extended by 1 bit, then the number of resistors in the fine ladder is not doubled, so the DAC operating speed is not slowed down. That is a substantial benefit of the level shift method of extending resolution of a dual resistor ladder DAC.
However, the bit level shifting circuitry in FIG. 2A has drawbacks. A major drawback is that the on-state switch resistance RDS(ON) of switches 24 and 25 has an impact on the DNL and INL performance of DAC 10-2. In DAC 10-2 of FIG. 2A, the switch ON resistance RDS(ON) between ladders (i.e. at the two input terminals 3-N and 3-(N+1) of fine ladder 5) is considered to provide a “minimum unit step” resolution of fine ladder 5. This requires the ON resistance of each MOS transistor switch to be equal to one fourth of the fine ladder unit resistance R2, that is, equal to:
                                          R                          DS              ⁡                              (                ON                )                                              =                                    1                                                k                  ′                                ⁢                                  W                  L                                ⁢                                  (                                                            V                      G                                        -                                          V                      S                                        -                                          V                      T                                                        )                                                      =                                          R                ⁢                                                                  ⁢                2                            4                                      ,                            Equation        ⁢                                  ⁢                  (          1          )                    where W/L is the channel-width-to-channel-length ratio of the MOS transistor switch, VG is the gate voltage of the MOS transistor switch, VS is source voltage of the MOS transistor switch, VT is its gate-to source turn-on threshold voltage, and k′ is a proportionality constant.
The channel resistance RDS(ON) of the switches SW(N) and SW(N+1) for connecting coarse ladder 4 to fine ladder 5, and the channel resistance of the switches 24 and 25 performing the above-mentioned bit level shifting, can not be adequately matched with the polycrystalline silicon R2 resistors in fine ladder 5. This is partly because N-channel transistors and poly resistors are implemented in different steps during wafer fabrication, and partly because they also have substantially different temperature coefficients. The inadequate matching results in substantial degradation of DNL and INL performance of prior art DAC 10-2.
Compared to DAC 10-1 in FIG. 1, the minimum step in fine ladder 5 in FIG. 2A Is represented by R2/2. Therefore, RDS(ON) of MOS transistor switches SW(N) and SW(N+1) is equal to 4×R2. It is difficult for the on-state channel resistance RDS(ON) of a MOS transistor switch to perfectly match the resistance of a polycrystalline silicon resistor with resistance R2, not only because the MOS switches and poly resistors are formed in different steps of the wafer fabrication process and have different temperature coefficients, but also because the channel resistances RDS(ON) are dependent on the source voltages Vs of the various MOS transistor switches SW(0), SW(1), . . . , SW(64) connected to the various nodes of the coarse ladder and therefore vary substantially.
The switch channel resistance RDS(ON) between ladders may be adjusted (by some amount) to provide some degree of matching with the resistance R2 by using switch size scaling, i.e., “W/L” scaling, based on Equation (1) and a known value of transistor source electrode voltage Vs. Unfortunately, such W/L scaling does not provide adequate matching. However, the switches 24 and 25 that perform the bit level shifting in fine ladder 5 usually are “exercised” in same way for every code generated by 8 LSB digital encoder 8. To minimize the effect of mismatching of switch resistance RDS(ON) and TC (temperature coefficient) effects on the DNL of DAC 10-2, the various switches must be designed with a very large W/L ratio. Unfortunately, a large switch occupies more integrated circuit chip area and causes greater charge injection. This may result in large voltage glitches in the DAC circuit and longer settling times during circuit operation.
Those skilled in the art understand that when an N-type MOS transistor switch is turned on, its channel region is inverted and electrons in the channel are expelled from the channel region when the MOS switch is suddenly turned off. The expelled electrons constitute “charge injection”, which generate the voltage glitches at the DAC output conductor 3. Therefore, large size MOS switch transistors are required to achieve good DNL in DAC 10-2 of FIG. 2A, but unfortunately this causes higher amounts of charge injection and consequently larger voltage glitches at the DAC output 3.
With reference now to FIG. 2B, there is shown a diagram of a high-level view of a dual-resistor ladder DAC 600, as shown in FIG. 6a of the above-mentioned commonly assigned '387 patent. The diagram shown in FIG. 2B illustrates the dual-resistor ladder DAC 600, wherein the dual-resistor ladder DAC 600 features transistors, preferably N-type MOS transistors, operating in a triode region and used as resistors in the fine resistor ladder portion of the dual-resistor ladder DAC 600. As discussed previously, the use of transistors rather than poly resistors can help to eliminate a source for impedance mismatch and therefore improve the DNL of the dual-resistor ladder DAC 600.
The dual-resistor ladder DAC 600 in FIG. 2B includes a coarse resistor ladder 605 comprised of N coarse resistor/switch banks, such as coarse resistor/switch bank 607. The number of coarse resistor/switch banks is dependent upon a number of binary digits decoded by a first decoder 610 in the coarse resistor ladder 605 and the number of binary digits decoded by a second decoder 611. For example, in a 12 bit dual-resistor ladder DAC, wherein six bits are decoded by the coarse resistor ladder 605 and six bits are decoded by a fine resistor ladder, with a resistor/switch bank of 16 resistors and 16 switches, four coarse resistor/switch banks may be needed. The first decoder 610 is used to select one out of the N coarse resistor/switch banks. Referring to the example discussed above, a 2-to-4 decoder is used to decode two of the six binary digits decoded by the coarse resistor ladder 605 to select one of the four coarse resistor/switch banks.
Every switch in the N coarse resistor/switch banks is coupled to one of two buses, shown in FIG. 2B as buses 615. The use of the bus 615 and associated two-level decoding circuitry can reduce the hardware and circuitry requirements of the decoder 610 used in the coarse resistor ladder and a first decoder 630 used in a fine resistor ladder. For example, in a coarse resistor ladder that uses one-level decoding, an associated decoder needs to select a single resistor, resulting in a decoder with a complexity that is on the order of 26=64, while using two-level decoding, the complexity of the decoder is on the order of 23+2323=16. A bank of switches, such as switch bank 620, one for each bus, couples the output of the switches in the N coarse resistor/switch banks to either a top terminal or a bottom terminal of the fine resistor ladder 625.
The fine resistor ladder 625 comprises M fine resistor/switch banks, such as fine resistor/switch bank 627. The number of fine resistor/switch banks in the fine resistor ladder 625 is dependent upon the number of binary digits decoded by the first decoder 630 of the fine resistor ladder 625 as well as the number of binary digits decoded by a second decoder 631. With reference back to the example discussed previously, if six bits are decoded by the fine resistor ladder 625 and each fine resistor/switch bank contains eight resistors and switches (one of the fine resistor/switch banks will contain one fewer resistor than the remaining M−1 fine resistor/switch banks), then eight fine resistor/switch banks are needed. The first decoder 630 can be used to select one of the M fine resistor/switch banks. Using the example discussed previously, the first decoder 630 is a 3-to-8 decoder. The first decoder 630 decodes three of the six binary digits provided to the fine resistor ladder 625 to select one of the eight fine resistor/switch banks. Again, the use of two-stage decoding and the fine resistor/switch banks in the fine resistor ladder 625 result in a reduction in the complexity of the digital circuitry compared to one-stage decoding. Each switch in the M fine resistor/switch banks is coupled to a bus 635 that allows the coupling of the switches to a fine-ladder switch bank 640. The fine ladder switch bank 640 permits the coupling of outputs of the switches in the M fine resistor/switch banks to an output of the dual-resistor ladder DAC 600. Using the example discussed previously, the second decoder 631 decodes the remaining three binary digits to select one of the eight outputs from the fine ladder switch bank 640 and provides it to the output of the dual-resistor ladder DAC 600.
Prior Art FIG. 2C is a copy of FIG. 7a of the above-mentioned commonly assigned '387 patent, in which series-connected MOS transistors, including transistors 716, 717, and 718 operated in their triode regions are utilized as the resistors in fine ladder 715, analogously to the series-connected resistors R2 in Prior Art FIG. 2A, and bit level shifting MOS transistor 720 is analogous to bit level shifting resistor 22 and its associated switch 24 in FIG. 2A, and bit level shifting MOS transistor 721 is analogous to bit level shifting resistor 21 and its associated switch 25 in FIG. 2A. The '387 patent teaches that the dual-resistor ladder of DAC 700 is not affected by changing the resistance of a top resistor and a bottom resistor and its fine resistor ladder 715 and there are no mismatches due to differences in temperature coefficients and voltage coefficients. The '387 patent notes that the “half resistance” of the top resistor cell including MOS resistors 718 and 721 and the half resistance of the bottom resistor cell including MOS resistors 717 and 720 closely match the resistance in the fine resistor ladder 715 over process and temperature variations and can greatly improve DNL performance.
A drawback of DAC 700 in FIG. 2C is that it only provides 1-bit level shifting. If a designer wishes to extend the DAC resolution by 1 bit resolution based on DAC 700, the number of resistors in either the coarse ladder or the fine ladder must be doubled, resulting in the previously mentioned substantially slower DAC operation.
It would be highly desirable to have a circuit and method to perform improved 2 bit level shifting (and higher bit level shifting) in a dual resistor ladder DAC to solve above mentioned problems.
Thus, there is an unmet need for a dual resistor ladder DAC and method which provide substantially improved signal level bit-shifting circuitry and operation so as to achieve substantially improved resolution and accuracy of the DAC.
There also is an unmet need for a dual resistor ladder DAC and method which provide substantially improved signal level bit-shifting circuitry and operation so as to achieve substantially improved resolution and accuracy of the DAC without increasing the output impedance and output capacitance of the DAC.
There also is an unmet need for a dual resistor ladder DAC and method which provide substantially improved signal level bit-shifting circuitry and operation so as to achieve substantially improved resolution and accuracy of the dual resistor ladder DAC by improving the matching of resistive elements within the DAC over a range of fabrication processes and temperatures.